corne-light-rev1.1.0
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42f0870649
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corne-light/pcb/corne-light-rescue.dcm
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3
corne-light/pcb/corne-light-rescue.dcm
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EESchema-DOCLIB Version 2.0
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#
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#End Doc Library
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corne-light/pcb/corne-light-rescue.lib
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corne-light/pcb/corne-light-rescue.lib
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EESchema-LIBRARY Version 2.4
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#encoding utf-8
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#
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# ProMicro-kbd
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#
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DEF ProMicro-kbd U 0 40 Y Y 1 F N
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F0 "U" 0 950 60 H V C CNN
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F1 "ProMicro-kbd" 0 -550 60 H V C CNN
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F2 "" 100 -1050 60 H V C CNN
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F3 "" 100 -1050 60 H V C CNN
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DRAW
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S -500 850 500 -450 0 1 0 N
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X TX 1 -700 750 200 R 50 50 1 1 B
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X E6 10 -700 -150 200 R 50 50 1 1 B
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X B4 11 -700 -250 200 R 50 50 1 1 B
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X B5 12 -700 -350 200 R 50 50 1 1 B
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X B6 13 700 -350 200 L 50 50 1 1 B
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X B2 14 700 -250 200 L 50 50 1 1 B
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X B3 15 700 -150 200 L 50 50 1 1 B
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X B1 16 700 -50 200 L 50 50 1 1 B
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X F7 17 700 50 200 L 50 50 1 1 B
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X F6 18 700 150 200 L 50 50 1 1 B
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X F5 19 700 250 200 L 50 50 1 1 B
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X RX 2 -700 650 200 R 50 50 1 1 B
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X F4 20 700 350 200 L 50 50 1 1 B
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X VCC 21 700 450 200 L 50 50 1 1 W
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X RST 22 700 550 200 L 50 50 1 1 I
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X GND 23 700 650 200 L 50 50 1 1 W
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X RAW 24 700 750 200 L 50 50 1 1 w
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X GND 3 -700 550 200 R 50 50 1 1 W
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X GND 4 -700 450 200 R 50 50 1 1 W
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X SDA 5 -700 350 200 R 50 50 1 1 B
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X SCL 6 -700 250 200 R 50 50 1 1 B
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X D4 7 -700 150 200 R 50 50 1 1 B
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X C6 8 -700 50 200 R 50 50 1 1 B
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X D7 9 -700 -50 200 R 50 50 1 1 B
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ENDDRAW
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ENDDEF
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#
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#End Library
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File diff suppressed because it is too large
Load Diff
@ -1,25 +1,6 @@
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update=2018年08月24日金曜日 18:16:26
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update=2019 November 05, Tuesday 00:04:59
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version=1
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last_client=kicad
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[pcbnew]
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version=1
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LastNetListRead=
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UseCmpFile=1
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PadDrill=0.600000000000
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PadDrillOvalY=0.600000000000
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PadSizeH=1.500000000000
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PadSizeV=1.500000000000
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PcbTextSizeV=1.500000000000
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PcbTextSizeH=1.500000000000
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PcbTextThickness=0.300000000000
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ModuleTextSizeV=1.000000000000
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ModuleTextSizeH=1.000000000000
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ModuleTextSizeThickness=0.150000000000
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SolderMaskClearance=0.000000000000
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SolderMaskMinWidth=0.000000000000
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DrawSegmentWidth=0.200000000000
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BoardOutlineThickness=0.100000000000
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ModuleOutlineThickness=0.150000000000
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[cvpcb]
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version=1
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NetIExt=net
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@ -28,3 +9,231 @@ version=1
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[eeschema]
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version=1
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LibDir=
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[pcbnew]
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version=1
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PageLayoutDescrFile=
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LastNetListRead=
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CopperLayerCount=2
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BoardThickness=1.6
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AllowMicroVias=0
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AllowBlindVias=0
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RequireCourtyardDefinitions=0
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ProhibitOverlappingCourtyards=1
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MinTrackWidth=0.2
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MinViaDiameter=0.4
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MinViaDrill=0.3
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MinMicroViaDiameter=0.2
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MinMicroViaDrill=0.09999999999999999
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MinHoleToHole=0.25
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TrackWidth1=0.25
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TrackWidth2=0.2032
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TrackWidth3=0.254
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TrackWidth4=0.5
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TrackWidth5=0.508
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ViaDiameter1=0.6
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ViaDrill1=0.4
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dPairWidth1=0.2
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dPairGap1=0.25
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dPairViaGap1=0.25
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SilkLineWidth=0.15
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SilkTextSizeV=1
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SilkTextSizeH=1
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SilkTextSizeThickness=0.15
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SilkTextItalic=0
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SilkTextUpright=1
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CopperLineWidth=0.15
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CopperTextSizeV=1.5
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CopperTextSizeH=1.5
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CopperTextThickness=0.3
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CopperTextItalic=0
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CopperTextUpright=1
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EdgeCutLineWidth=0.2
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CourtyardLineWidth=0.05
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OthersLineWidth=0.15
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OthersTextSizeV=1
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OthersTextSizeH=1
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OthersTextSizeThickness=0.15
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OthersTextItalic=0
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OthersTextUpright=1
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SolderMaskClearance=0.2
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SolderMaskMinWidth=0
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SolderPasteClearance=0
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SolderPasteRatio=-0
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[pcbnew/Layer.F.Cu]
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Name=F.Cu
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Type=0
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Enabled=1
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[pcbnew/Layer.In1.Cu]
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Name=In1.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In2.Cu]
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Name=In2.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In3.Cu]
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Name=In3.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In4.Cu]
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Name=In4.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In5.Cu]
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Name=In5.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In6.Cu]
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Name=In6.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In7.Cu]
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Name=In7.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In8.Cu]
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Name=In8.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In9.Cu]
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Name=In9.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In10.Cu]
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Name=In10.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In11.Cu]
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Name=In11.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In12.Cu]
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Name=In12.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In13.Cu]
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Name=In13.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In14.Cu]
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Name=In14.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In15.Cu]
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Name=In15.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In16.Cu]
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Name=In16.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In17.Cu]
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Name=In17.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In18.Cu]
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Name=In18.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In19.Cu]
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Name=In19.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In20.Cu]
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Name=In20.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In21.Cu]
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Name=In21.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In22.Cu]
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Name=In22.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In23.Cu]
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Name=In23.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In24.Cu]
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Name=In24.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In25.Cu]
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Name=In25.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In26.Cu]
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Name=In26.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In27.Cu]
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Name=In27.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In28.Cu]
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Name=In28.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In29.Cu]
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Name=In29.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.In30.Cu]
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Name=In30.Cu
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Type=0
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Enabled=0
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[pcbnew/Layer.B.Cu]
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Name=B.Cu
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Type=0
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Enabled=1
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[pcbnew/Layer.B.Adhes]
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Enabled=1
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[pcbnew/Layer.F.Adhes]
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Enabled=1
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[pcbnew/Layer.B.Paste]
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Enabled=1
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[pcbnew/Layer.F.Paste]
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Enabled=1
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[pcbnew/Layer.B.SilkS]
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Enabled=1
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[pcbnew/Layer.F.SilkS]
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Enabled=1
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[pcbnew/Layer.B.Mask]
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Enabled=1
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[pcbnew/Layer.F.Mask]
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Enabled=1
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[pcbnew/Layer.Dwgs.User]
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Enabled=1
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[pcbnew/Layer.Cmts.User]
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Enabled=1
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[pcbnew/Layer.Eco1.User]
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Enabled=1
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[pcbnew/Layer.Eco2.User]
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Enabled=1
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[pcbnew/Layer.Edge.Cuts]
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Enabled=1
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[pcbnew/Layer.Margin]
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Enabled=1
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[pcbnew/Layer.B.CrtYd]
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Enabled=1
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[pcbnew/Layer.F.CrtYd]
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Enabled=1
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[pcbnew/Layer.B.Fab]
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Enabled=1
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[pcbnew/Layer.F.Fab]
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Enabled=1
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[pcbnew/Layer.Rescue]
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Enabled=0
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[pcbnew/Netclasses]
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[pcbnew/Netclasses/Default]
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Name=Default
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Clearance=0.2
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TrackWidth=0.25
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ViaDiameter=0.6
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ViaDrill=0.4
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uViaDiameter=0.3
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uViaDrill=0.1
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dPairWidth=0.2
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dPairGap=0.25
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dPairViaGap=0.25
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File diff suppressed because it is too large
Load Diff
4
corne-light/pcb/fp-lib-table
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4
corne-light/pcb/fp-lib-table
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(fp_lib_table
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(lib (name locallib)(type KiCad)(uri /Users/foostan/src/github.com/foostan/crkbd-secret/corne-plus/locallib.pretty)(options "")(descr ""))
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(lib (name MX_Alps_Hybrid)(type KiCad)(uri /Users/foostan/src/github.com/foostan/crkbd-secret/corne-plus/MX_Alps_Hybrid.pretty)(options "")(descr ""))
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)
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(sym_lib_table
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(lib (name corne-light-rescue)(type Legacy)(uri ${KIPRJMOD}/corne-light-rescue.lib)(options "")(descr ""))
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)
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