corne-light-rev1.1.0

This commit is contained in:
foostan 2019-11-05 02:43:24 +09:00
parent 42f0870649
commit 1418305d72
7 changed files with 81801 additions and 12128 deletions

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EESchema-DOCLIB Version 2.0
#
#End Doc Library

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EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# ProMicro-kbd
#
DEF ProMicro-kbd U 0 40 Y Y 1 F N
F0 "U" 0 950 60 H V C CNN
F1 "ProMicro-kbd" 0 -550 60 H V C CNN
F2 "" 100 -1050 60 H V C CNN
F3 "" 100 -1050 60 H V C CNN
DRAW
S -500 850 500 -450 0 1 0 N
X TX 1 -700 750 200 R 50 50 1 1 B
X E6 10 -700 -150 200 R 50 50 1 1 B
X B4 11 -700 -250 200 R 50 50 1 1 B
X B5 12 -700 -350 200 R 50 50 1 1 B
X B6 13 700 -350 200 L 50 50 1 1 B
X B2 14 700 -250 200 L 50 50 1 1 B
X B3 15 700 -150 200 L 50 50 1 1 B
X B1 16 700 -50 200 L 50 50 1 1 B
X F7 17 700 50 200 L 50 50 1 1 B
X F6 18 700 150 200 L 50 50 1 1 B
X F5 19 700 250 200 L 50 50 1 1 B
X RX 2 -700 650 200 R 50 50 1 1 B
X F4 20 700 350 200 L 50 50 1 1 B
X VCC 21 700 450 200 L 50 50 1 1 W
X RST 22 700 550 200 L 50 50 1 1 I
X GND 23 700 650 200 L 50 50 1 1 W
X RAW 24 700 750 200 L 50 50 1 1 w
X GND 3 -700 550 200 R 50 50 1 1 W
X GND 4 -700 450 200 R 50 50 1 1 W
X SDA 5 -700 350 200 R 50 50 1 1 B
X SCL 6 -700 250 200 R 50 50 1 1 B
X D4 7 -700 150 200 R 50 50 1 1 B
X C6 8 -700 50 200 R 50 50 1 1 B
X D7 9 -700 -50 200 R 50 50 1 1 B
ENDDRAW
ENDDEF
#
#End Library

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update=2018年08月24日金曜日 18:16:26
update=2019 November 05, Tuesday 00:04:59
version=1
last_client=kicad
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
[cvpcb]
version=1
NetIExt=net
@ -28,3 +9,231 @@ version=1
[eeschema]
version=1
LibDir=
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=
CopperLayerCount=2
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.2
MinViaDiameter=0.4
MinViaDrill=0.3
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.25
TrackWidth2=0.2032
TrackWidth3=0.254
TrackWidth4=0.5
TrackWidth5=0.508
ViaDiameter1=0.6
ViaDrill1=0.4
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.15
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
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CopperTextItalic=0
CopperTextUpright=1
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OthersTextSizeH=1
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OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0.2
SolderMaskMinWidth=0
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
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[pcbnew/Layer.In2.Cu]
Name=In2.Cu
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[pcbnew/Layer.In3.Cu]
Name=In3.Cu
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[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
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[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
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[pcbnew/Layer.In6.Cu]
Name=In6.Cu
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[pcbnew/Layer.In7.Cu]
Name=In7.Cu
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[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
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[pcbnew/Layer.In9.Cu]
Name=In9.Cu
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[pcbnew/Layer.In10.Cu]
Name=In10.Cu
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[pcbnew/Layer.In11.Cu]
Name=In11.Cu
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[pcbnew/Layer.In12.Cu]
Name=In12.Cu
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[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
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[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
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[pcbnew/Layer.In28.Cu]
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Type=0
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[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
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[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
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[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
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[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.2
TrackWidth=0.25
ViaDiameter=0.6
ViaDrill=0.4
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25

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(fp_lib_table
(lib (name locallib)(type KiCad)(uri /Users/foostan/src/github.com/foostan/crkbd-secret/corne-plus/locallib.pretty)(options "")(descr ""))
(lib (name MX_Alps_Hybrid)(type KiCad)(uri /Users/foostan/src/github.com/foostan/crkbd-secret/corne-plus/MX_Alps_Hybrid.pretty)(options "")(descr ""))
)

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(sym_lib_table
(lib (name corne-light-rescue)(type Legacy)(uri ${KIPRJMOD}/corne-light-rescue.lib)(options "")(descr ""))
)