diff --git a/corne-ultralight/pcb/corne-ultralight.kicad_pcb b/corne-ultralight/pcb/corne-ultralight.kicad_pcb index 406087d..91754be 100644 --- a/corne-ultralight/pcb/corne-ultralight.kicad_pcb +++ b/corne-ultralight/pcb/corne-ultralight.kicad_pcb @@ -1,4 +1,4 @@ -(kicad_pcb (version 20211014) (generator pcbnew) +(kicad_pcb (version 20221018) (generator pcbnew) (general (thickness 1.6) @@ -54,14 +54,15 @@ (grid_origin 31.7125 74.445) (pcbplotparams (layerselection 0x00310ff_ffffffff) + (plot_on_all_layers_selection 0x0000000_00000000) (disableapertmacros false) (usegerberextensions true) (usegerberattributes false) (usegerberadvancedattributes false) (creategerberjobfile false) - (svguseinch false) + (dashed_line_dash_ratio 12.000000) + (dashed_line_gap_ratio 3.000000) (svgprecision 6) - (excludeedgelayer true) (plotframeref false) (viasonmask false) (mode 1) @@ -180,33 +181,39 @@ (net 90 "unconnected-(PSW2-Pad3)") (footprint "kbd:ResetSW_1side" (layer "F.Cu") - (tedit 5F8C82CB) (tstamp 00000000-0000-0000-0000-00005c2803c0) + (tstamp 00000000-0000-0000-0000-00005c2803c0) (at 156.0125 76.817432 -90) (property "Sheetfile" "corne-ultralight.kicad_sch") (property "Sheetname" "") (path "/00000000-0000-0000-0000-00005c25f978") (attr through_hole) (fp_text reference "RSW2" (at 0 2.55 90) (layer "F.SilkS") hide - (effects (font (size 1 1) (thickness 0.15))) + (effects (font (size 1 1) (thickness 0.15))) (tstamp c3d3bda0-ec99-4f41-844b-45c4b586cadc) ) (fp_text value "SW_PUSH" (at 0 -2.55 90) (layer "F.Fab") - (effects (font (size 1 1) (thickness 0.15))) + (effects (font (size 1 1) (thickness 0.15))) (tstamp d5c9cb5a-8d6b-4c59-8ee7-5f0619f2ada7) ) (fp_text user "RESET" (at 0 0 90) (layer "F.SilkS") - (effects (font (size 1 1) (thickness 0.15))) + (effects (font (size 1 1) (thickness 0.15))) (tstamp feb14930-bafe-46c6-8fca-6877f5a6d2f0) ) - (fp_line (start 2.85 -1.6) (end 2.85 -1.35) (layer "F.SilkS") (width 0.15) (tstamp 12b4f8fe-19d4-471e-9782-9d5ae63268ef)) - (fp_line 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+5717,37 @@ ) (footprint "kbd:D3_TH_SMD_v2" (layer "B.Cu") - (tedit 5FAC0B14) (tstamp 00000000-0000-0000-0000-00005dbe1cdf) + (tstamp 00000000-0000-0000-0000-00005dbe1cdf) (at 33.1875 64.92 90) (descr "Resitance 3 pas") (tags "R") (property "Sheetfile" "corne-ultralight.kicad_sch") (property "Sheetname" "") (path "/00000000-0000-0000-0000-00005a5e2d2c") - (autoplace_cost180 10) (attr through_hole) (fp_text reference "D8" (at 0.55 0 90) (layer "B.Fab") hide - (effects (font (size 0.5 0.5) (thickness 0.125)) (justify mirror)) + (effects (font (size 0.5 0.5) (thickness 0.125)) (justify mirror)) (tstamp 4d067ae9-e6ce-47a6-89da-78d7c105f46d) ) (fp_text value "D" (at -0.55 0 90) (layer "B.Fab") hide - (effects (font (size 0.5 0.5) (thickness 0.125)) (justify mirror)) + (effects (font (size 0.5 0.5) (thickness 0.125)) (justify mirror)) (tstamp 016156bf-2546-4007-bde4-0dcec11e8c38) ) - (fp_line (start 0.5 -0.5) (end -0.4 0) (layer "B.SilkS") (width 0.15) (tstamp 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(justify mirror)) + (effects (font (size 0.5 0.5) (thickness 0.125)) (justify mirror)) (tstamp 9db0cc91-b65e-483f-88e5-b09aa5d15e7a) ) (fp_text value "D" (at -0.55 0 90) (layer "B.Fab") hide - (effects (font (size 0.5 0.5) (thickness 0.125)) (justify mirror)) + (effects (font (size 0.5 0.5) (thickness 0.125)) (justify mirror)) (tstamp 3e88045f-c049-4db9-966d-fe46faf858b3) ) - (fp_line (start 0.5 -0.5) (end -0.4 0) (layer "B.SilkS") (width 0.15) (tstamp 3317305b-ab2c-4f45-8091-870b4bab3a9f)) - (fp_line (start -0.5 0.5) (end -0.5 -0.5) (layer "B.SilkS") (width 0.15) (tstamp 58edfe02-ca60-49b3-b37a-332b65c455ac)) - (fp_line (start -0.4 0) (end 0.5 0.5) (layer "B.SilkS") (width 0.15) (tstamp 9c428c1b-7892-430f-aa5e-c849b8af3f96)) - (fp_line (start 0.5 0.5) (end 0.5 -0.5) (layer "B.SilkS") (width 0.15) (tstamp ea9dfa5d-c83e-4dbc-b6a5-0032ebe9db8c)) - (pad "1" thru_hole rect locked (at -3 0 90) (size 1.778 1.3) (drill 0.8128) (layers *.Cu "F.Mask") + (fp_line (start -0.5 0.5) (end -0.5 -0.5) + (stroke (width 0.15) (type solid)) (layer "B.SilkS") (tstamp 58edfe02-ca60-49b3-b37a-332b65c455ac)) + (fp_line (start -0.4 0) (end 0.5 0.5) + (stroke (width 0.15) (type solid)) (layer "B.SilkS") (tstamp 9c428c1b-7892-430f-aa5e-c849b8af3f96)) + (fp_line (start 0.5 -0.5) (end -0.4 0) + (stroke (width 0.15) (type solid)) (layer "B.SilkS") (tstamp 3317305b-ab2c-4f45-8091-870b4bab3a9f)) + (fp_line (start 0.5 0.5) (end 0.5 -0.5) + (stroke (width 0.15) (type solid)) (layer "B.SilkS") (tstamp ea9dfa5d-c83e-4dbc-b6a5-0032ebe9db8c)) + (pad "1" thru_hole rect (at -3 0 90) (size 1.778 1.3) (drill 0.8128) (layers "*.Cu" "F.Mask") (net 5 "row2") (pinfunction "K") (pintype "passive") (tstamp 3eba5206-6bde-435e-86c5-0a5b97cc59d4)) - (pad "1" smd rect locked (at -1.775 0 270) (size 1.4 1.3) (layers "B.Cu" "B.Paste" "B.Mask") + (pad "1" smd rect (at -1.775 0 270) (size 1.4 1.3) (layers "B.Cu" "B.Paste" "B.Mask") (net 5 "row2") (pinfunction "K") (pintype "passive") (tstamp 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"Net-(D17-Pad2)") (pinfunction "A") (pintype "passive") (tstamp 8edd151b-0526-4b55-a5e2-5b81e24660bb)) (model "Diodes_SMD.3dshapes/SMB_Handsoldering.wrl" (offset (xyz 0 0 0)) @@ -5118,35 +6077,38 @@ ) (footprint "kbd:D3_TH_SMD_v2" (layer "B.Cu") - (tedit 5FAC0B14) (tstamp 00000000-0000-0000-0000-00005dc6adf6) + (tstamp 00000000-0000-0000-0000-00005dc6adf6) (at 71.1875 78.915 90) (descr "Resitance 3 pas") (tags "R") (property "Sheetfile" "corne-ultralight.kicad_sch") (property "Sheetname" "") (path "/00000000-0000-0000-0000-00005a5e35e1") - (autoplace_cost180 10) (attr through_hole) (fp_text reference "D16" (at 0.55 0 90) (layer "B.Fab") hide - (effects (font (size 0.5 0.5) (thickness 0.125)) (justify mirror)) + (effects (font (size 0.5 0.5) (thickness 0.125)) (justify mirror)) (tstamp a780a3f4-0f09-4ec9-a38e-f2bcbd7304c7) ) (fp_text value "D" (at -0.55 0 90) (layer "B.Fab") hide - (effects (font (size 0.5 0.5) (thickness 0.125)) (justify mirror)) + (effects (font (size 0.5 0.5) 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00000000-0000-0000-0000-00005dc6afca) + (tstamp 00000000-0000-0000-0000-00005dc6afca) (at 71.1875 40.915 90) (descr "Resitance 3 pas") (tags "R") (property "Sheetfile" "corne-ultralight.kicad_sch") (property "Sheetname" "") (path "/00000000-0000-0000-0000-00005a5e29bf") - (autoplace_cost180 10) (attr through_hole) (fp_text reference "D4" (at 0.55 0 90) (layer "B.Fab") hide - (effects (font (size 0.5 0.5) (thickness 0.125)) (justify mirror)) + (effects (font (size 0.5 0.5) (thickness 0.125)) (justify mirror)) (tstamp 021c01bd-dd0f-4049-b5b4-48f1562229f7) ) (fp_text value "D" (at -0.55 0 90) (layer "B.Fab") hide - (effects (font (size 0.5 0.5) (thickness 0.125)) (justify mirror)) + (effects (font (size 0.5 0.5) (thickness 0.125)) (justify mirror)) (tstamp 8f7b8ace-cd85-4b75-9742-22cc6b519920) ) - (fp_line (start 0.5 0.5) (end 0.5 -0.5) (layer "B.SilkS") (width 0.15) (tstamp 04190ddc-2d6b-4231-8611-3d07f0565d03)) - (fp_line (start -0.4 0) (end 0.5 0.5) (layer "B.SilkS") (width 0.15) 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(type solid)) (layer "B.SilkS") (tstamp f373d871-58a0-4ada-bde2-81533b219593)) + (fp_line (start -0.4 0) (end 0.5 0.5) + (stroke (width 0.15) (type solid)) (layer "B.SilkS") (tstamp ca2d48f7-afaf-4ced-add5-6dd91112e7f3)) + (fp_line (start 0.5 -0.5) (end -0.4 0) + (stroke (width 0.15) (type solid)) (layer "B.SilkS") (tstamp c273e58e-7528-4c55-a18e-848b4b246b79)) + (fp_line (start 0.5 0.5) (end 0.5 -0.5) + (stroke (width 0.15) (type solid)) (layer "B.SilkS") (tstamp 849153de-4900-456c-86fc-c38d1c173314)) + (pad "1" thru_hole rect (at -3 0 90) (size 1.778 1.3) (drill 0.8128) (layers "*.Cu" "F.Mask") (net 1 "row0") (pinfunction "K") (pintype "passive") (tstamp d98f8c24-99d4-4afe-8a9f-e6f04eea88b6)) - (pad "2" smd rect locked (at 1.775 0 270) (size 1.4 1.3) (layers "B.Cu" "B.Paste" "B.Mask") + (pad "1" smd rect (at -1.775 0 270) (size 1.4 1.3) (layers "B.Cu" "B.Paste" "B.Mask") + (net 1 "row0") (pinfunction "K") (pintype "passive") (tstamp 95daa323-c0c5-4289-9c0f-628bda332669)) + (pad "2" smd rect (at 1.775 0 270) (size 1.4 1.3) (layers "B.Cu" "B.Paste" "B.Mask") (net 6 "Net-(D3-Pad2)") (pinfunction "A") (pintype "passive") (tstamp 1298b6a0-ceef-4e15-b6a1-adb08b374cae)) - (pad "2" thru_hole oval locked (at 3 0 90) (size 1.778 1.3) (drill 0.8128) (layers *.Cu "F.Mask") + (pad "2" thru_hole oval (at 3 0 90) (size 1.778 1.3) (drill 0.8128) (layers "*.Cu" "F.Mask") (net 6 "Net-(D3-Pad2)") (pinfunction "A") (pintype "passive") (tstamp 201715e6-b21b-482c-a614-7c639c477aa5)) (model "Diodes_SMD.3dshapes/SMB_Handsoldering.wrl" (offset (xyz 0 0 0)) @@ -5622,34 +6617,37 @@ ) (footprint "kbd:D3_TH_SMD_v2" (layer "B.Cu") - (tedit 5FAC0B14) (tstamp 00000000-0000-0000-0000-00005dc6b03f) + (tstamp 00000000-0000-0000-0000-00005dc6b03f) (at 30.1875 45.916875 90) (descr "Resitance 3 pas") (tags "R") (property "Sheetfile" "corne-ultralight.kicad_sch") (property "Sheetname" "") (path "/00000000-0000-0000-0000-00005a5e2b5b") - (autoplace_cost180 10) (attr through_hole) (fp_text reference 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00000000-0000-0000-0000-00005dc6f6c8) + (tstamp 00000000-0000-0000-0000-00005dc6f6c8) (at 267.684847 83.920432 90) (descr "Resitance 3 pas") (tags "R") (property "Sheetfile" "corne-ultralight.kicad_sch") (property "Sheetname" "") (path "/00000000-0000-0000-0000-00005c25f8f3") - (autoplace_cost180 10) (attr through_hole) (fp_text reference "D35" (at 0.55 0 90) (layer "B.Fab") hide - (effects (font (size 0.5 0.5) (thickness 0.125)) (justify mirror)) + (effects (font (size 0.5 0.5) (thickness 0.125)) (justify mirror)) (tstamp ba6fc35c-fc27-410e-9101-1cf101870fbf) ) (fp_text value "D" (at -0.55 0 90) (layer "B.Fab") hide - (effects (font (size 0.5 0.5) (thickness 0.125)) (justify mirror)) + (effects (font (size 0.5 0.5) (thickness 0.125)) (justify mirror)) (tstamp 51b61763-e2d5-4481-8491-f8a75c54ed4c) ) - (fp_line (start 0.5 0.5) (end 0.5 -0.5) (layer "B.SilkS") (width 0.15) (tstamp 205b62ce-f493-4efa-97d1-04ac2c0fddba)) - (fp_line (start -0.5 0.5) (end -0.5 -0.5) (layer "B.SilkS") (width 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"high_contrast_mode": 0, "net_color_mode": 1, "opacity": { + "images": 0.6, "pads": 1.0, "tracks": 1.0, "vias": 1.0, @@ -39,7 +41,6 @@ 11, 12, 13, - 14, 15, 16, 17, @@ -60,7 +61,9 @@ 33, 34, 35, - 36 + 36, + 39, + 40 ], "visible_layers": "fffffff_ffffffff", "zone_display_mode": 1 diff --git a/corne-ultralight/pcb/corne-ultralight.kicad_pro b/corne-ultralight/pcb/corne-ultralight.kicad_pro index 3076dfe..275b726 100644 --- a/corne-ultralight/pcb/corne-ultralight.kicad_pro +++ b/corne-ultralight/pcb/corne-ultralight.kicad_pro @@ -1,5 +1,6 @@ { "board": { + "3dviewports": [], "design_settings": { "defaults": { "board_outline_line_width": 0.19999999999999998, @@ -63,20 +64,26 @@ "rule_severities": { "annular_width": "error", "clearance": "error", + "connection_width": "warning", "copper_edge_clearance": "ignore", + "copper_sliver": "warning", "courtyards_overlap": "error", "diff_pair_gap_out_of_range": "error", "diff_pair_uncoupled_length_too_long": "error", "drill_out_of_range": "error", "duplicate_footprints": "warning", "extra_footprint": "warning", + "footprint": "error", "footprint_type_mismatch": "error", "hole_clearance": "error", "hole_near_hole": "ignore", "invalid_outline": "error", + "isolated_copper": "warning", "item_on_disabled_layer": "error", "items_not_allowed": "error", "length_out_of_range": "error", + "lib_footprint_issues": "warning", + "lib_footprint_mismatch": "warning", "malformed_courtyard": "error", "microvia_drill_out_of_range": "error", "missing_courtyard": "ignore", @@ -86,9 +93,14 @@ "padstack": "error", "pth_inside_courtyard": "ignore", "shorting_items": "error", + "silk_edge_clearance": "warning", "silk_over_copper": "warning", "silk_overlap": "warning", "skew_out_of_range": "error", + "solder_mask_bridge": "error", + "starved_thermal": "error", + "text_height": "warning", + "text_thickness": "warning", "through_hole_pad_without_hole": "error", "too_many_vias": "error", "track_dangling": "warning", @@ -97,7 +109,6 @@ "unconnected_items": "error", "unresolved_variable": "error", "via_dangling": "warning", - "zone_has_empty_net": "error", "zones_intersect": "error" }, "rule_severitieslegacy_courtyards_overlap": true, @@ -107,18 +118,63 @@ "allow_microvias": false, "max_error": 0.005, "min_clearance": 0.0, + "min_connection": 0.0, "min_copper_edge_clearance": 0.09999999999999999, "min_hole_clearance": 0.25, "min_hole_to_hole": 0.25, "min_microvia_diameter": 0.19999999999999998, "min_microvia_drill": 0.09999999999999999, + "min_resolved_spokes": 2, "min_silk_clearance": 0.0, + "min_text_height": 0.7999999999999999, + "min_text_thickness": 0.08, "min_through_hole_diameter": 0.3, "min_track_width": 0.19999999999999998, "min_via_annular_width": 0.049999999999999996, "min_via_diameter": 0.39999999999999997, + "solder_mask_to_copper_clearance": 0.0, "use_height_for_length_calcs": true }, + "teardrop_options": [ + { + "td_allow_use_two_tracks": true, + "td_curve_segcount": 5, + "td_on_pad_in_zone": false, + "td_onpadsmd": true, + "td_onroundshapesonly": false, + "td_ontrackend": false, + "td_onviapad": true + } + ], + "teardrop_parameters": [ + { + "td_curve_segcount": 0, + "td_height_ratio": 1.0, + "td_length_ratio": 0.5, + "td_maxheight": 2.0, + "td_maxlen": 1.0, + "td_target_name": "td_round_shape", + "td_width_to_size_filter_ratio": 0.9 + }, + { + "td_curve_segcount": 0, + "td_height_ratio": 1.0, + "td_length_ratio": 0.5, + "td_maxheight": 2.0, + "td_maxlen": 1.0, + "td_target_name": "td_rect_shape", + "td_width_to_size_filter_ratio": 0.9 + }, + { + "td_curve_segcount": 0, + "td_height_ratio": 1.0, + "td_length_ratio": 0.5, + "td_maxheight": 2.0, + "td_maxlen": 1.0, + "td_target_name": "td_track_end", + "td_width_to_size_filter_ratio": 0.9 + } + ], "track_widths": [ 0.0, 0.2032, @@ -135,7 +191,8 @@ "zones_allow_external_fillets": false, "zones_use_no_outline": true }, - "layer_presets": [] + "layer_presets": [], + "viewports": [] }, "boards": [], "cvpcb": { @@ -357,7 +414,7 @@ "net_settings": { "classes": [ { - "bus_width": 12.0, + "bus_width": 12, "clearance": 0.2, "diff_pair_gap": 0.25, "diff_pair_via_gap": 0.25, @@ -371,10 +428,10 @@ "track_width": 0.25, "via_diameter": 0.6, "via_drill": 0.4, - "wire_width": 6.0 + "wire_width": 6 }, { - "bus_width": 12.0, + "bus_width": 12, "clearance": 1e-05, "diff_pair_gap": 1e-05, "diff_pair_via_gap": 0.25, @@ -383,16 +440,15 @@ "microvia_diameter": 0.2, "microvia_drill": 0.1, "name": "Min", - "nets": [], "pcb_color": "rgba(0, 0, 0, 0.000)", "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.2, "via_diameter": 0.4, "via_drill": 0.3, - "wire_width": 6.0 + "wire_width": 6 }, { - "bus_width": 12.0, + "bus_width": 12, "clearance": 0.2, "diff_pair_gap": 0.25, "diff_pair_via_gap": 0.25, @@ -401,26 +457,45 @@ "microvia_diameter": 0.3, "microvia_drill": 0.1, "name": "Power", - "nets": [ - "+BATT", - "+BATTA", - "GND", - "GNDA", - "Net-(BATJ1-Pad2)", - "Net-(BATJ3-Pad2)" - ], "pcb_color": "rgba(0, 0, 0, 0.000)", "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.5, "via_diameter": 0.8, "via_drill": 0.4, - "wire_width": 6.0 + "wire_width": 6 } ], "meta": { - "version": 2 + "version": 3 }, - "net_colors": null + "net_colors": null, + "netclass_assignments": null, + "netclass_patterns": [ + { + "netclass": "Power", + "pattern": "+BATT" + }, + { + "netclass": "Power", + "pattern": "+BATTA" + }, + { + "netclass": "Power", + "pattern": "GND" + }, + { + "netclass": "Power", + "pattern": "GNDA" + }, + { + "netclass": "Power", + "pattern": "Net-(BATJ1-Pad2)" + }, + { + "netclass": "Power", + "pattern": "Net-(BATJ3-Pad2)" + } + ] }, "pcbnew": { "last_paths": { diff --git a/corne-ultralight/pcb/gateron-ks27.pretty/gateron-ks27-choc-v1-mx-1.5u.kicad_mod b/corne-ultralight/pcb/gateron-ks27.pretty/gateron-ks27-choc-v1-mx-1.5u.kicad_mod index f4d186b..b1e5029 100644 --- a/corne-ultralight/pcb/gateron-ks27.pretty/gateron-ks27-choc-v1-mx-1.5u.kicad_mod +++ b/corne-ultralight/pcb/gateron-ks27.pretty/gateron-ks27-choc-v1-mx-1.5u.kicad_mod @@ -26,6 +26,8 @@ (pad "" np_thru_hole circle (at 5.22 -4.2) (size 0.9906 0.9906) (drill 0.9906) (layers F&B.Cu *.Mask) (tstamp f2a44eaf-666f-422c-bb4d-a717499c3d1a)) (pad "" np_thru_hole circle (at 5.5 0) (size 1.7018 1.7018) (drill 1.7018) (layers F&B.Cu *.Mask) (tstamp f565cf54-67ba-4424-8d47-087433645499)) (pad "" np_thru_hole circle (at -5.5 0) (size 1.7018 1.7018) (drill 1.7018) (layers F&B.Cu *.Mask) (tstamp fe4869dc-e96e-4bb4-a38d-2ca990635f2d)) + (pad "" np_thru_hole circle (at -5.08 0 48.0996) (size 1.75 1.75) (drill 1.75) (layers *.Cu *.Mask)) + (pad "" np_thru_hole circle (at 5.08 0 48.0996) (size 1.75 1.75) (drill 1.75) (layers *.Cu *.Mask)) (pad "1" thru_hole circle (at 3.81 2.54) (size 2.5 2.5) (drill 1.5) (layers *.Cu *.Mask) (tstamp 2d6db888-4e40-41c8-b701-07170fc894bc)) (pad "1" thru_hole circle (at 2.6 5.75) (size 2.5 2.5) (drill 1.5) (layers *.Cu *.Mask) (tstamp babeabf2-f3b0-4ed5-8d9e-0215947e6cf3)) (pad "1" thru_hole circle (at 0 5.9) (size 2.5 2.5) (drill 1.5) (layers *.Cu *.Mask) (tstamp edc9ab4f-487a-48dc-95f2-4d87f0e9cf9e)) diff --git a/corne-ultralight/pcb/gateron-ks27.pretty/gateron-ks27-choc-v1-mx.kicad_mod b/corne-ultralight/pcb/gateron-ks27.pretty/gateron-ks27-choc-v1-mx.kicad_mod index cd84242..79ccc64 100644 --- a/corne-ultralight/pcb/gateron-ks27.pretty/gateron-ks27-choc-v1-mx.kicad_mod +++ b/corne-ultralight/pcb/gateron-ks27.pretty/gateron-ks27-choc-v1-mx.kicad_mod @@ -26,6 +26,8 @@ (pad "" np_thru_hole circle (at 5.22 -4.2) (size 0.9906 0.9906) (drill 0.9906) (layers F&B.Cu *.Mask) (tstamp f2a44eaf-666f-422c-bb4d-a717499c3d1a)) (pad "" np_thru_hole circle (at 5.5 0) (size 1.7018 1.7018) (drill 1.7018) (layers F&B.Cu *.Mask) (tstamp f565cf54-67ba-4424-8d47-087433645499)) (pad "" np_thru_hole circle (at -5.5 0) (size 1.7018 1.7018) (drill 1.7018) (layers F&B.Cu *.Mask) (tstamp fe4869dc-e96e-4bb4-a38d-2ca990635f2d)) + (pad "" np_thru_hole circle (at -5.08 0 48.0996) (size 1.75 1.75) (drill 1.75) (layers *.Cu *.Mask)) + (pad "" np_thru_hole circle (at 5.08 0 48.0996) (size 1.75 1.75) (drill 1.75) (layers *.Cu *.Mask)) (pad "1" thru_hole circle (at 3.81 2.54) (size 2.5 2.5) (drill 1.5) (layers *.Cu *.Mask) (tstamp 2d6db888-4e40-41c8-b701-07170fc894bc)) (pad "1" thru_hole circle (at 2.6 5.75) (size 2.5 2.5) (drill 1.5) (layers *.Cu *.Mask) (tstamp babeabf2-f3b0-4ed5-8d9e-0215947e6cf3)) (pad "1" thru_hole circle (at 0 5.9) (size 2.5 2.5) (drill 1.5) (layers *.Cu *.Mask) (tstamp edc9ab4f-487a-48dc-95f2-4d87f0e9cf9e))